Since the invention of integrated circuits, the semiconductor industry has experienced a continuous rapid growth due to constant improvements in the integration density of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.). For the most part, the improvement in the integration density has come from repeated reductions in minimum feature size, allowing for more components to be integrated into a given chip area.
These integration improvements are essentially two-dimensional (2D) in nature, in that the volume occupied by the integrated components is essentially on the surface of the semiconductor wafer. Although dramatic improvement in lithography has resulted in considerable improvements in 2D integrated circuit formation, there are physical limitations to the density that can be achieved in two dimensions. One of these limitations is the minimum size needed to make these components. Also, when more devices are put into one chip, more complex designs are required.
An additional limitation comes from the significant increase in the number and the length of interconnections between devices as the number of devices increases. When the number and length of interconnections increase, both circuit RC delay and power consumption increase.
Among the efforts for resolving the above-discussed limitations, stacking dies is a commonly used method, in which through-wafer vias (TWV) are used to connect dies. FIG. 1 illustrates a cross-sectional view of a portion of a wafer having TWVs. Semiconductor substrate 2 includes integrated circuits (not shown) formed thereon. Interconnect structure 4, which includes dielectric layers, metal lines, vias (not shown) and bonding pads 6, is formed over semiconductor substrate 2. TWVs 8 are formed in semiconductor substrate 2. Bonding pads 10 are electrically connected to TWVs 8.
The formation of TWVs includes two categories, via-first approach and via-last approach. In the via-first approach, TWVs are formed from the topside (the side on which the integrated circuits are formed). After the integrated circuits and interconnect structure 4 are formed, the backside of substrate 2 is grinded, exposing TWVs 8. Bonding pads 10 are then formed. In the via-last approach, after the integrated circuits and interconnect structure 4 are formed, TWVs 8 are formed by drilling or etching the backside of substrate 2 to form openings, and then filling the openings with metals.
Currently, there are no effective alignment methods available for the via-last approach, and thus TWVs 8 may deviate from the desired positions. Furthermore, the thickness of semiconductor substrate 2 is typically significantly greater than the dimension of the integrated circuits and connection structure 4, and thus any tilting of TWVs 8 will result in significant deviation of topsides 12 of TWVs 8, resulting in circuit failure. Currently, the misalignment problem can only be found at wafer-sorting stage. At this time, a significant number of problematic wafers may have already been made.
Conventionally, misaligned wafers are analyzed using transmission electron microscopy (TEM) or scanning electron microscopy (SEM), which result in the damage of the wafers. However, if the misalignment is due to the tilting of TWVs, even TEM/SEM may not reveal problems unless the TEM/SEM is performed along the right plane. Therefore, new methods are needed to reveal TWV formation problems during early stages.